1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication technology. More particularly, the present invention relates to a modified gate structure for non-volatile memory and its method of fabricating the same.
2. Description of the Related Art
Non-volatile memory devices have been widely applied in electrical appliances, computers, instruments, etc., on account of a programmable facility and static storage after power-off FIG. 1 schematically a conventional gate structure of a non-volatile memory in a cross-sectional view. In the drawing, reference numeral 10 designates a semiconductor substrate. A first silicon dioxide layer 12 having a thickness of about 80.about.200 .ANG. and a dielectric constant of about 3.9 is formed on the substrate 10 on which a first polysilicon layer 13 is deposited as a floating gate of a non-volatile memory device. Then, an O/N/O layer 14 is formed on the first polysilicon layer 13. For example, the O/N/O layer 14 is configured with a three-layer structure comprising a second silicon dioxide layer of about 50 .ANG., a silicon nitride layer of about 200 .ANG., and a third silicon dioxide layer of about 50 .ANG.. Then, a second polysilicon layer 19 is deposited on the O/N/O layer 14 to be a control gate of the non-volatile memory device.
FIG. 2 schematically depicts an equivalent circuit diagram of the conventional gate structure pertaining to capacitive elements as shown FIG. 1, wherein the substrate 10 is grounded. In FIG. 2, C.sub.1 represents the capacitance between the control gate 19 and the floating gate 13, C.sub.2 represents the capacitance between the floating gate 13 and the substrate 10, and both are connected in series. V.sub.1 designates an voltage applied to the control gate, which is coupled to the floating gate 13 through the capacitance C.sub.1 as a voltage V.sub.2, wherein V.sub.2 =[C.sub.1 /(C.sub.1 +C.sub.2)]V.sub.1. Accordingly, the applying voltage V.sub.1 should be so high enough that the coupled voltage V.sub.2 is able to induce electrons injection by means of tunneling effect into the floating gate 13.
General speaking, a non-volatile memory device with the conventional gate structure depicted in FIG. 1 should be powered by quite a high applying voltage V.sub.1 (e.g., 12 V or more) inconvenient for circuit designers and users.
To lower the desired applying voltage V.sub.1, but sustain enough coupled voltage V.sub.2 for inducing tunneling effect, increasing of the capacitance C.sub.1 is a feasible approach. Usually, two ways are utilized to increase the capacitance C.sub.1 by: (1) increasing the capacitance area and (2) replacing the O/N/O with high dielectric constant material such as tantalum oxide (Ta.sub.2 O.sub.5) or BST (BaSrTiO.sub.3). However, the former will consume additional layout area which is unfavorable to integrated circuit miniaturization. The latter may deteriorate tantalum oxide (Ta.sub.2 O.sub.5) or BST while generally subjected to an annealing treatment after the formation of tantalum oxide or BST wherein oxygen contained therein may react with silicon to form silicon dioxide. Furthermore, reducing gas such as nitrogen employed during the subsequent processes causes tantalum oxide or BST defects through which a leakage current flows.